As consumer devices have gotten smaller and smaller in response to consumer demand, the individual components of these devices and their connecting pathways that form the consumer devices have decreased in size as well. Semiconductor devices, which make up a major component of devices such as mobile phones, computer tablets, and the like, have been pressured to become smaller and smaller, with a corresponding pressure on the individual devices (e.g., transistors, resistors, capacitors, etc.) and their connecting pathways (e.g., interconnecting lines) within the semiconductor devices to also be reduced in size.
One potential problem of this drive to reduce the size of the individual devices is a bottleneck that has formed regarding the interconnections that electrically connect the individual active devices within the semiconductor device. In particular, as the individual interconnects continue to be reduced along with the individual transistors, resistors, etc., previously containable issues with process alignments have arisen.
Accordingly, new processes and procedures are needed to help overcome these problems.